PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 11H: CDRC Interrupt Enable
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
LCVE
LOSE
0
0
0
0
0
X
X
X
B8ZSE
Z8DE
Z16DE
Unused
Unused
Unused
The bit positions LCVE,LOSE,B8ZSE, Z8DE and Z16DE (bits 7 to 3) of this
register are interrupt enables to select which of the status events (Line Code
Violation , Loss Of Signal, B8ZS Pattern, 8 Zeros, or 16 Zeros), either singly or in
combination, are enabled to generate an interrupt on the microprocessor INTB
pin when they are detected. A logic 1 bit in the corresponding bit position enables
the detection of these signals to generate an interrupt; a logic 0 bit in the
corresponding bit position disables that signal from generating an interrupt.
When the T1XC is reset, LCVE,LOSE,B8ZSE, Z8DE, and Z16DE are set to logic
0, disabling these events from generating an interrupt.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
98
PMC [ PMC-SIERRA, INC ]
