PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 14H: XPLS Line Length Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R
RPT
SM
0
0
0
1
0
0
0
0
0
R
1
R
0
R/W
R/W
R/W
ILS[2]
ILS[1]
ILS[0]
This register allows software to select the length of cable that XPLS is required to
drive and to enable generation of user-programmable output templates.
RPT:
The RPT bit enables the 4-bit DAC codes contained in the Register
Programmable Template CODE registers to generate the output waveform.
When RPT is set to a logic 1, the internal user-programmable XPLS CODE
registers supply the DAC codes used to generate the waveform. When RPT is
set to logic 0, the DAC codes contained in the internal ROM generate the
output waveform in accordance with the line length selected.
SM:
The SM bit allows software to select one of eight waveform templates by
enabling the ILS[2:0] select bits. When SM is set to logic 1, the ILS[2:0] bit
positions select one of eight waveform templates. When SM is set to logic 0,
the ILS[2:0] bits are ignored and the default 330-440 ft. waveform template is
selected.
The eight available templates are selected via the following values of ILS[2:0]:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
100
PMC [ PMC-SIERRA, INC ]
