PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 10H: CDRC Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
AMI
0
X
X
X
X
0
Unused
Unused
Unused
Unused
ALGSEL
Unused
Unused
R/W
X
X
AMI:
The alternate mark inversion (AMI) bit specifies the line code of the incoming
DS1 signal. A logic 1 selects AMI line code; a logic 0 selects B8ZS line code.
ALGSEL:
The Algorithm Select (ALGSEL) bit specifies the algorithm used by the DPLL
for clock and data recovery.The choice of algorithm determines the high
frequency input jitter tolerance of the CDRC. When ALGSEL is set to logic 1,
the CDRC jitter tolerance is increased to approach 0.5UIpp for jitter
frequencies above 20KHz. When ALGSEL is set to logic 0, the jitter tolerance
is increased for frequencies below 20KHz (i.e. the tolerance is improved by
20% over that of ALGSEL=1 at these frequencies), but the tolerance
approaches 0.4UIpp at the higher frequencies.
Note that in Line Loopback mode (Register 0AH, LINELB bit =1) AGSEL
should be set to logic 0 for optimal performance.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
97
PMC [ PMC-SIERRA, INC ]
