PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Register 12H: CDRC Interrupt Status
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
R
R
R
LCVI
LOSI
X
X
X
X
X
X
X
X
B8ZSI
Z8DI
Z16DI
Unused
Unused
LOS
R
The bit positions LCVI,LOSI,B8ZSI, Z8DI, and Z16DI (bits 7 to 3) of this register
indicate which of the status events generated an interrupt. A logic 1 in these bit
positions indicate that the corresponding event was detected and generated an
interrupt; a logic 0 in these bit positions indicate that no corresponding event has
been detected. The bit positions LCVI, B8ZSI, Z8DI, and Z16DI are set on the
assertion of the corresponding event. LOSI is set on any change of state of the
LOS alarm. Bits LCVI, LOSI, B8ZSI, Z8DI, and Z16DI are cleared by reading this
register.The current state of the LOS alarm can be determined by reading bit 0
of this register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
99
PMC [ PMC-SIERRA, INC ]
