PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
the previous word value; PSB[8] is toggled only under the following conditions (all
other bit value transitions leave PSB[8] unchanged):
Table 6
- Phase Status Word Operation
Previous PSB[7:5]
Current PSB[7:5]
Affect on PSB[8]
000
000
11X
1X1
11X
1X1
000
000
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The contents of the Phase Status Word registers (address 0EH and 0FH) are
internally updated on each receive line data frame pulse; a write to either T1XC
register address 0EH or 0FH must be performed to freeze the contents before
this register and the Phase Status Word (MSB) register can be read.The correct
sequence for reading the contents of the Phase Status Word are:
1. write to register address 0EH or 0FH
2. read register address 0FH (read Phase Status Word MSB)
3. read register address 0EH (read Phase Status Word LSB)
This write-before-read is analogous to the latching of performance monitor
counter values in PMON, and is required to ensure that the phase status word
value remains valid during the µP read. It is important to read the MSB register
before the LSB register because, once the Phase Status Word (LSB) register has
been read, the phase status word counter is unfrozen and the contents may
change immediately.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
95
PMC [ PMC-SIERRA, INC ]
