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PM4341A-QI 参数 Datasheet PDF下载

PM4341A-QI图片预览
型号: PM4341A-QI
PDF下载: 下载PDF文件 查看货源
内容描述: T1成帧器/收发器 [T1 FRAMER/TRANSCEIVER]
分类和应用: 数字传输控制器电信集成电路电信电路
文件页数/大小: 288 页 / 981 K
品牌: PMC [ PMC-SIERRA, INC ]
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PM4341AT1XC  
DATA SHEET  
PMC-900602  
ISSUE 7  
T1 FRAMER/TRANSCEIVER  
Register 0EH:T1XC Phase Status Word (LSB)  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R
R
R
R
R
R
R
R
PSB[7]  
PSB[6]  
PSB[5]  
PSB[4]  
PSB[3]  
PSB[2]  
PSB[1]  
PSB[0]  
X
X
X
X
X
X
X
X
This register contains the least significant byte, PSB[7:0], of the 9-bit phase  
status word.The 9-bit phase status word indicates the relative phase difference  
between the received DS-1 line timing (available on RCLKO) and a system timing  
which uses either a 2.048MHz backplane (input on BRCLK, with BRX2M=1 in  
Reg. 00H) or a 1.544MHz backplane (input on BRCLK, with BRX2M=0). By  
utilizing the value of the phase status word, the system timing can be locked to  
the receive line timing via an external software controlled phase-locked-loop.  
The least significant 8 bits contained in this register indicate a count value (either  
0-255 for BRX2M=1 or 0-192 for BRX2M=0) of the number of system backplane  
clock cycles between successive 125µs frame pulses.The most significant 5 bits  
(PSB[7:3]) represent a channel number (0-31 for BRX2M=1 or 0-23 for  
BRX2M=0) and the least significant 3 bits (PSB[2:0]) represent the bit number  
within the channel (0-7). The count value corresponds to the location within the  
system frame where the receive line-timed frame pulse occurred. If the received  
line clock frequency is higher on average than the system clock frequency, the  
phase status word value will be seen to decrease during successive register  
reads. If the received line clock frequency is lower on average than the system  
clock frequency, the phase status word value will be seen to increase during  
successive register reads.  
The 9th bit of the Phase Status Word indicates the "frame count" and will toggle  
when two successive 8-bit counter values straddle a frame boundary.The  
PSB[8] bit will toggle when the bit and channel count indicated by PSB[7:0]  
exceeds channel 31, bit 7 (when BRX2M=1; or channel 23, bit 7 when  
BRX2M=0) or the count goes below channel 0, bit 0. This is determined by  
comparing the PSB[7:5] bits of the current phase status word value to those of  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
94  
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