PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
Figure 12
-TransmitTiming Options
FIFO output
data clock
TCLKO
FIFO input
data clock
DJAT
FIFO
0
1
0
1
BTXCLK
BTX2M
BTCLK
0
1
OCLKSEL1
2.048MHz
Clock
gapper
OCLKSEL0
1
0
Smooth 1.544MHz
0
1
00
11
"Jitter-free"
1.544MHz
DJAT
PLL
01
SMCLKO
Smooth
12.352
MHz
0
PLLREF[1:0]
10
RCLKO
TCLKI
1
"Jitter-free"
12.352MHz
÷ 8
XPLS
0
1
XCLK
TCLKISEL
XCLKSEL
(37.056MHz
or
12.352MHz)
0
1
"High-speed" clock for CDRC
& FRMR (=12.352MHz)
0
1
"High-speed" clock for ELST,
SIGX, TPSC & RPSC (≥6x
max backplane clockrate)
÷ 2
HSBPSEL
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
85
PMC [ PMC-SIERRA, INC ]
