PM4341AT1XC
DATA SHEET
PMC-900602
ISSUE 7
T1 FRAMER/TRANSCEIVER
InputTransmit
Data
Bit Settings
XCLK Freq
Affect on Output
Transmit Data
Backplane
transmit data
timed to BTCLK.
HSBPSEL =0
XCLKSEL =0
OCLKSEL1 =0
OCLKSEL0 =1
37.056MHz
No jitter
attenuation.
TCLKO is equal
to TCLKI (useful
for higher rate
MUX
PLLREF1
PLLREF0
=X
=X
applications).
TCLKISEL =0
SMCLKO =0
12.352MHz
37.056MHz
12.352MHz
Same as above.
XCLKSEL =1
TCLKISEL =1
SMCLKO
=1
Backplane
transmit data
timed to BTCLK.
HSBPSEL =0
XCLKSEL =0
OCLKSEL1 =0
OCLKSEL0 =0
TCLKI is a jitter-
free 12.352MHz
clock.TCLKO is
equal to TCLKI÷8.
PLLREF1
PLLREF0
=X
=X
Same as above.
TCLKISEL =0
SMCLKO =1
XCLKSEL =1
HSBPSEL =0
XCLKSEL =1
OCLKSEL1 =0
OCLKSEL0 =0
Backplane
transmit data
timed to BTCLK.
jitter-free
12.352MHz
XCLK is a jitter-
free 12.352MHz
clock.TCLKO is
equal to XCLK÷8.
PLLREF1
PLLREF0
=X
=X
TCLKISEL =1
SMCLKO =1
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
83
PMC [ PMC-SIERRA, INC ]
