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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
Frequency Range  
In the non-attenuating mode for T1 rates, that is, when the FIFO is within one UI  
of overrunning or under running, the tracking range is 1.48 to 1.608 MHz. The  
guaranteed linear operating range for the jittered input clock is 1.544 MHz ± 200  
Hz with worst case jitter (29 UIpp) and maximum XCLK frequency offset (± 100  
ppm). The nominal range is 1.544 MHz ± 963 Hz with no jitter or XCLK  
frequency offset.  
In the non-attenuating mode for E1 rates the tracking range is 1.963 to 2.133  
MHz. The guaranteed linear operating range for the jittered input clock is 2.048  
MHz ± 1278 Hz with worst case jitter (42 UIpp) and maximum XCLK frequency  
offset (± 100 ppm).  
9.19 Timing Options (TOPS)  
The Timing Options block provides a means of selecting the source of the  
internal input clock to the TJAT block, the reference clock for the TJAT digital  
PLL, and the clock source used to derive the transmit clock to the M13 mux.  
9.20 Pseudo Random Binary Sequence Generation and Detection (PRBS)  
The Pseudo Random Binary Sequence Generator/Detector (PRBS) block is a  
software selectable PRBS generator and checker for 211-1, 215-1 or 220-1 PRBS  
polynomials for use in the T1 and E1 links. PRBS patterns may be generated in  
either the transmit or receive directions, and detected in the opposite direction.  
The PRBS block can perform an auto synchronization to the expected PRBS  
pattern and accumulates the total number of bit errors in two 24-bit counters.  
The error count accumulates over the interval defined by to the Global PMON  
Update Register. When an accumulation is forced, the holding register is  
updated, and the counter reset to begin accumulating for the next interval. The  
counter is reset in such a way that no events are missed. The data is then  
available in the Error Count registers until the next accumulation.  
9.21 Pseudo Random Pattern Generation and Detection (PRGD)  
The Pseudo Random Pattern Generator/Detector (PRGD) block is a software  
programmable test pattern generator, receiver, and analyzer for the DS3  
payload. Patterns may be generated in the transmit direction, and detected in  
the receive direction. Two types of ITU-T O.151 compliant test patterns are  
provided : pseudo-random and repetitive.  
PROPRIETARY AND CONFIDENTIAL  
77  
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