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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
The PRGD can be programmed to generate any pseudo-random pattern with  
length up to 232-1 bits or any user programmable bit pattern from 1 to 32 bits in  
length. In addition, the PRGD can insert single bit errors or a bit error rate  
-1  
-7  
between 10 to 10 .  
The PRGD can be programmed to check for the generated pseudo random  
pattern. The PRGD can perform an auto synchronization to the expected pattern  
and accumulates the total number of bits received and the total number of bit  
errors in two 32-bit counters. The counters accumulate either over intervals  
defined by writes to the Pattern Detector registers, upon writes to the Global  
PMON Update Register or automatically once a second. When an accumulation  
is forced, the holding registers are updated, and the counters reset to begin  
accumulating for the next interval. The counters are reset in such a way that no  
events are missed. The data is then available in the holding registers until the  
next accumulation.  
9.22 DS3 Framer (DS3-FRMR)  
The DS3 Framer (DS3-FRMR) Block integrates circuitry required for decoding a  
B3ZS-encoded signal and framing to the resulting DS3 bit stream. The  
DS3-FRMR is directly compatible with the M23 and C-bit parity DS3 applications.  
The DS3-FRMR decodes a B3ZS-encoded signal and provides indications of line  
code violations. The B3ZS decoding algorithm and the LCV definition can be  
independently chosen through software. A loss of signal (LOS) defect is also  
detected for B3ZS encoded streams. LOS is declared when inputs RPOS and  
RNEG contain zeros for 175 consecutive RCLK cycles. LOS is removed when  
the ones density on RPOS and/or RNEG is greater than 33% for 175 ±1 RCLK  
cycles.  
The framing algorithm examines five F-bit candidates simultaneously. When at  
least one discrepancy has occurred in each candidate, the algorithm examines  
the next set of five candidates. When a single F-bit candidate remains in a set,  
the first bit in the supposed M-subframe is examined for the M-frame alignment  
signal (i.e., the M-bits, M1, M2, and M3 are following the 010 pattern). Framing  
is declared, and out-of-frame is removed, if the M-bits are correct for three  
consecutive M-frames while no discrepancies have occurred in the F-bits.  
During the examination of the M-bits, the X-bits and P-bits are ignored. The  
algorithm gives a maximum average reframe time of 1.5 ms.  
While the DS3-FRMR is synchronized to the DS3 M-frame, the F-bit and M-bit  
positions in the DS3 stream are examined. An out-of-frame defect is detected  
when 3 F-bit errors out of 8 or 16 consecutive F-bits are observed (as selected  
by the M3O8 bit in the DS3 FRMR Configuration Register), or when one or more  
PROPRIETARY AND CONFIDENTIAL  
78  
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