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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
8
PIN DESCRIPTION  
Pin Name  
Type Pin Function  
No.  
DS3 Line Side Interface  
RCLK  
Input W5  
Receive Input Clock (RCLK). RCLK provides the  
receive direction timing. RCLK is a DS3, nominally a  
44.736 MHz, 50% duty cycle clock input.  
RPOS/RDAT  
Input Y7  
Input AB6  
Output AA7  
Positive Input Pulse (RPOS). RPOS represents the  
positive pulses received on the B3ZS-encoded DS3  
when dual rail input format is selected.  
Receive Data Input (RDAT). RDAT represents the  
NRZ (unipolar) DS3 input data stream when single rail  
input format is selected.  
RPOS and RDAT are sampled on the rising edge of  
RCLK by default and may be enabled to be sampled  
on the falling edge of RCLK by setting the RFALL bit in  
the DS3 Master Receive Line Options register.  
Negative Input Pulse (RNEG). RNEG represents the  
negative pulses received on the B3ZS-encoded DS3  
when dual rail input format is selected.  
Line code violation (RLCV). RLCV represents receive  
line code violations when single rail input format is  
selected.  
RNEG and RLCV are sampled on the rising edge of  
RCLK by default and may be enabled to be sampled  
on the falling edge of RCLK by setting the RFALL bit in  
the DS3 Master Receive Line Options register.  
Transmit Clock (TCLK). TCLK provides timing for  
circuitry downstream of the DS3 transmitter of the  
TECT3. TCLK is nominally a 44.736 MHz, 50% duty  
cycle clock.  
RNEG/RLCV  
TCLK  
PROPRIETARY AND CONFIDENTIAL  
26  
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