STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
Pin Name
Type Pin Function
No.
XCLK/VCLK
Input E20
Crystal Clock Input (XCLK). This 24 times T1 or E1
clock provides timing for many of the T1 and E1
portions of TECT3. XCLK is nominally a 37.056 MHz ±
32ppm, 50% duty cycle clock when configured for T1
modes and is nominally a 49.152 MHz ± 32ppm, 50%
duty cycle clock when configured for E1 modes.
This clock is required for all operating modes of the
TECT3.
Test Vector Clock (VCLK). This signal is used during
production testing.
DS3 System Side Interface
RGAPCLK/RSCLK Output Y3
Framer Recovered Gapped Clock (RGAPCLK).
RGAPCLK is valid when the TECT3 is configured as a
DS3 framer by setting the OPMODE[1:0] bits in the
Global Configuration register and the RXGAPEN bit in
the DS3 Master Unchannelized Interface Options
register.
RGAPCLK is the recovered clock and timing reference
for RDATO. RGAPCLK is held either high or low
during bit positions which correspond to overhead.
Framer Recovered Clock (RSCLK). RSCLK is valid
when the TECT3 is configured as a DS3 framer by
setting the OPMODE[1:0] bits in the Global
Configuration register.
RSCLK is the recovered clock and timing reference for
RDATO, RFPO/RMFPO, and ROVRHD.
This signal shares a signal pin with ICLK[1]. When
enabled for unchannelized DS3 operation this signal
will be RGAPCLK/RSCLK, otherwise it will be ICLK[1].
RDATO
Output AA5
Framer Receive Data (RDATO). RDATO is valid when
the TECT3 is configured as a DS3 framer by setting
the OPMODE[1:0] bits in the Global Configuration
register. RDATO is the received data aligned to
RFPO/RMFPO and ROVRHD.
RDATO is updated on either the falling or rising edge
of RGAPCLK or RSCLK, depending on the value of
PROPRIETARY AND CONFIDENTIAL
28
PMC [ PMC-SIERRA, INC ]
