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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
Signals, Far End Receive Failure and idle signal can be inserted using either  
internal registers or can be configured for automatic insertion upon received  
errors. When M23 operation is selected, the C-bit Parity ID bit (the first C-bit of  
the first M sub-frame) is forced to toggle so that downstream equipment will not  
confuse an M23-formatted stream with stuck-at-1 C-bits for C-bit Parity  
application. Transmit timing is from an external reference or from the receive  
direction clock.  
The TECT3 also supports diagnostic options which allow it to insert, when  
appropriate for the transmit framing format, parity or path parity errors, F-bit  
framing errors, M-bit framing errors, invalid X or P-bits, line code violations,  
all-zeros, AIS, Remote Alarm Indications, and Remote End Alarms. A Pseudo  
Random Binary Sequence (PRBS) can be inserted into a DS3 payload and  
checked in the receive DS3 payload for bit errors. A fixed 100100… pattern is  
available for insertion directly into the B3ZS encoder for proper pulse mask  
shape verification.  
When configured in DS3 multiplexer mode, seven 6312 kbit/s data streams are  
demultiplexed and multiplexed into and out of the DS3 signal. Bit stuffing and  
rate adaptation is performed. The C-bits are set appropriately, with the option of  
inserting DS2 loopback requests. Interrupts can be generated upon detection of  
loopback requests in the received DS3. AIS may be inserted in the any of the  
6312 kbit/s tributaries in both the multiplex and demultiplex directions. C-bit  
parity is supported by sourcing a 6.3062723 MHz clock, which corresponds to a  
stuffing ratio of 100%.  
Framing to the demultiplexed 6312 kbit/s data streams supports DS2 (ANSI  
TI.107) frame formats. The maximum average reframe time is 7ms for DS2. Far  
end receive failure is detected and M-bit and F-bit errors are accumulated. The  
DS2 framer is an off-line framer, indicating both OOF and COFA events. Error  
events (FERF, MERR, FERR, PERR, RAI, framing word errors) are still indicated  
while the DS2 framer is indicating OOF, based on the previous alignment.  
Each of the seven 6312 kbit/s multiplexers may be independently configured to  
multiplex and demultiplex four 1544 kbit/s DS1s into and out of a DS2 formatted  
signal. Tributary frequency deviations are accommodated using internal FIFOs  
and bit stuffing. The C-bits are set appropriately, with the option of inserting DS1  
loopback requests. Interrupts can be generated upon detection of loopback  
requests in the received DS2. AIS may be inserted in any of the low speed  
tributaries in both multiplex and demultiplex directions.  
When configured as a DS3 framer the unchannelized payload of the DS3 link is  
available to an external device.  
PROPRIETARY AND CONFIDENTIAL  
23  
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