STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
In synchronous backplane systems 8Mb/s H-MVIP interfaces are provided for
access to 672 DS0 channels, channel associated signaling (CAS) for all 672
DS0 channels and common channel signaling (CCS) for all 28 T1s. The DS0
data channel H-MVIP and CAS H-MVIP access is multiplexed with the serial
PCM interface pins. The CCS signaling H-MVIP interface is independent of the
DS0 channel and CAS H-MVIP access. The use of any of the H-MVIP interfaces
requires that common clocks and frame pulse be used along with T1 slip buffers.
A Scaleable Bandwidth Interconnect (SBI) high density byte serial system
interface provides higher levels of integration and dense interconnect. The SBI
bus interconnects up to 84 T1s both synchronously or asynchronously. The SBI
allows transmit timing to be mastered by either the TECT3 or link layer device
connected to the SBI bus. This interconnect allows up to 3 TECT3s to be
connected in parallel to provide the full complement of 84 T1s of traffic. In
addition to framed T1s, the TECT3 can transport unframed T1 links and framed
or unframed DS3 links over the SBI bus.
When configured as a DS3 multiplexer/demultiplexer or DS3 framer, the TECT3
accepts and outputs either or both digital B3ZS-encoded bipolar and unipolar
signals compatible with M23 and C-bit parity applications.
In the DS3 receive direction, the TECT3 frames to DS3 signals with a maximum
-3
average reframe time of 1.5 ms in the presence of 10 bit error rate and detects
line code violations, loss of signal, framing bit errors, parity errors, C-bit parity
errors, far end block errors, AIS, far end receive failure and idle code. The DS3
framer is an off-line framer, indicating both out of frame (OOF) and change of
frame alignment (COFA) events. The error events (C-BIT, FEBE, etc.) are still
indicated while the framer is OOF, based on the previous frame alignment. When
in C-bit parity mode, the Path Maintenance Data Link and the Far End Alarm and
Control (FEAC) channels are extracted. HDLC receivers are provided for Path
Maintenance Data Link support. In addition, valid bit-oriented codes in the FEAC
channels are detected and are available through the microprocessor port.
Error event accumulation is also provided by the TECT3. Framing bit errors, line
code violations, excessive zeros occurrences, parity errors, C-bit parity errors,
and far end block errors are accumulated. Error accumulation continues even
while the off-line framers are indicating OOF. The counters are intended to be
-3
polled once per second, and are sized so as not to saturate at a 10 bit error
rate. Transfer of count values to holding registers is initiated through the
microprocessor interface.
In the DS3 transmit direction, the TECT3 inserts DS3 framing, X and P bits.
When enabled for C-bit parity operation, bit-oriented code transmitters and
HDLC transmitters are provided for insertion of the FEAC channels and the Path
Maintenance Data Links into the appropriate overhead bits. Alarm Indication
PROPRIETARY AND CONFIDENTIAL
22
PMC [ PMC-SIERRA, INC ]
