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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
Figure 54: Framer Mode DS3 Receive Output Stream  
RSCLK  
INFO INFO INFO  
INFO INFO INFO  
INFO INFO  
INFO  
INFO INFO  
RDATO  
F
4
X
1
X
2
INFO INFO INFO  
RFPO/RMFPO  
ROVRHD  
Figure 55: Framer Mode DS3 Receive Output Stream with RGAPCLK  
RGAPCLK  
INFO INFO  
INFO  
INFO INFO INFO  
INFO INFO  
INFO  
INFO INFO  
RDATO  
INFO INFO INFO  
The DS3 Framer Only Mode Receive Output Stream diagram (Figure 54) shows  
the format of the outputs RDATO, RFPO/RMFPO, RSCLK ROVRHD when the  
OPMODE[1:0] bits are set to “DS3 Framer Only mode” in the Global  
Configuration register. Figure 54 shows the data streams when the TECT3 is  
configured for the DS3 receive format. If the RXMFPO bit in the DS3 Master  
Unchannelized Interface Options register is logic 0, RFPO is valid and will pulse  
high for one RSCLK cycle on first bit of each M-subframe with alignment to the  
RDATO data stream. If the RXMFPO register bit is a logic 1 (as shown Figure  
54), RMFPO is valid and will pulse high on the X1 bit of the RDATO data output  
stream. ROVRHD will be high for every overhead bit position on the RDATO  
data stream. Figure 55 shows the output data stream with RGAPCLK in place of  
RSCLK when the RXGAPEN bit in the DS3 Master Unchannelized Interface  
Options register set to logic 1. RGAPCLK remains high during the overhead bit  
positions.  
PROPRIETARY AND CONFIDENTIAL  
186  
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