STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
13.4 SBI ADD Bus Interface Timing
The SBI ADD bus functional timing for the transfer of tributaries, whether T1 or
DS3, is the same as for the SBI DROP bus. The only difference is that the SBI
ADD bus has one additional signal: the SAJUST_REQ output. The
SAJUST_REQ signal is used to by the TECT3 in SBI master timing mode to
provide transmit timing to SBI link layer devices.
Figure 58: SBI ADD Bus Justification Request Functional Timing
SSS
SREFCLK
SSS
SC1FP
SSS
SADATA[7:0]
SAPL
DS-3 #1 DS-3 #2DS-3 #3DS-3 #1
C1
H3
H3
H3
SSS
SSS
SSS
SSS
SAV5
SADP
SAJUST_REQ
Figure 58 illustrates the operation of the SBI ADD Bus, using positive and
negative justification requests as an example. (The responses to the justification
requests would take effect during the next multi-frame.) The negative
justification request occurs on the DS-3#3 tributary when SAJUST_REQ is
asserted high during the H3 octet. The positive justification occurs on the DS-3#2
tributary when SAJUST_REQ is asserted high during the first DS-3#2 octet after
the H3 octet.
13.5 Egress H-MVIP Link Timing
The timing relationship of the common 8M H-MVIP clock, CMV8MCLK, frame
pulse clock, CMVFPC, data, MVED[x], CASED[x] or CCSED, and frame pulse,
CMVFPB, signals of a link configured for 8.192 Mbps H-MVIP operation with a
type 0 frame pulse is shown in Figure 59. The falling edges of each CMVFPC
are aligned to a falling edge of the corresponding CMV8MCLK for 8.192 Mbps H-
MVIP operation. The TECT3 samples CMVFPB low on the falling edge of
CMVFPC and references this point as the start of the next frame. The TECT3
samples the data provided on MVED[x], CASED[x] and CCSED at the ¾ point of
the data bit using the rising edge of CMV8MCLK as indicated for bit 1 (B1) of
time-slot 1 (TS 1) in Figure 59. B1 is the most significant bit and B8 is the least
significant bit of each octet.
PROPRIETARY AND CONFIDENTIAL
188
PMC [ PMC-SIERRA, INC ]
