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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
13.2 DS3 System Side Interface Timing  
Figure 52: Framer Mode DS3 Transmit Input Stream  
TICLK or RCLK  
INFO 82 INFO 83 INFO 84  
INFO 82 INFO 83 INFO 84  
TDATI  
X2  
INFO 82 INFO 83 INFO 84  
INFO 1 INFO 2  
INFO 1 INFO 2 INFO 3  
X1  
F4  
TFPI/TMFPI  
TFPO/TMFPO  
Figure 53: Framer Mode DS3 Transmit Input Stream With TGAPCLK  
TGAPCLK  
TDATI  
INFO 1  
INFO 2 INFO 3  
INFO 4  
INFO 83 INFO 84  
INFO 1  
INFO 83 INFO 84  
INFO 1  
INFO 2 INFO 3  
INFO 81 INFO 82 INFO 83  
The Framer Mode DS3 Transmit Input Stream diagram (Figure 52) shows the  
expected format of the inputs TDATI and TFPI/TMFPI along with TICLK and the  
output TFPO/TMFPO when the OPMODE[1:0] bits are set to “DS3 Framer Only  
mode” in the Global Configuration register. If the TXMFPI bit in the DS3 Master  
Unchannelized Interface Options register is logic 0, then TFPI is valid, and the  
TECT3 will expect TFPI to pulse for every DS3 overhead bit with alignment to  
TDATI. If the TXMFPI register bit is logic 1, then TMFPI is valid, and the TECT3  
will expect TMFPI to pulse once every DS3 M-frame with alignment to TDATI. If  
the TXMFPO bit in the DS3 Master Unchannelized Interface Options register is  
logic 0, then TFPO is valid, and the TECT3 will pulse TFPO once every 85 TICLK  
cycles, providing upstream equipment with a reference DS3 overhead pulse. If  
the TXMFPO register bit is logic 1, then TMFPO is valid and the TECT3 will pulse  
TMFPO once every 4760 TICLK cycles, providing upstream equipment with a  
reference M-frame pulse. The alignment of TFPO or TMFPO is arbitrary. There  
is no set relationship between TFPO/TMFPO and TFPI/TMFPI. When the DS3  
interface is loop timed by setting the LOOPT bit in the DS3 Master Data Source  
register, RCLK replaces TICLK as the transmit timing reference and all timing is  
relative to RCLK.  
The TGAPCLK output is available in place of TFPO/TMFPO when the TXGAPEN  
bit in the DS3 Master Unchannelized Interface Options register is set to logic 1,  
as in Figure 53. TGAPCLK remains high during the overhead bit positions.  
TDATI is sampled on the active edge of TGAPCLK when TXGAPEN is set to  
logic 1 and on the active edge of TICLK when TXGAPEN is set to logic 0. The  
TDATIFALL bit in the DS3 Master Unchannelized Interface Options register  
selects the active edge of TICLK or TGAPCLK for sampling TDATI.  
PROPRIETARY AND CONFIDENTIAL  
185