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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
Sꢀ Provides Red, Yellow, and AIS alarm integration.  
Sꢀ Provides ESF bit-oriented code detection and an HDLC/LAPD interface for  
terminating the ESF facility data link.  
Sꢀ Indicates signaling state change, and two superframes of signaling debounce  
on a per-DS0 basis.  
Sꢀ Provides an HDLC interface with 128 bytes of buffering for terminating the  
facility data link.  
Sꢀ Provides performance monitoring counters sufficiently large as to allow  
performance monitor counter polling at a minimum rate of once per second.  
Optionally, updates the performance monitoring counters and interrupts the  
microprocessor once per second, timed to the receive line.  
Sꢀ Provides an optional elastic store which may be used to time the ingress  
streams to a common clock and frame alignment, or to facilitate per-DS0  
loopbacks.  
Sꢀ Provides DS-1 robbed bit signaling extraction, with optional data inversion,  
programmable idle code substitution, digital milliwatt code substitution, bit  
fixing, and two superframes of signaling debounce on a per-channel basis.  
Sꢀ A pseudo-random sequence user selectable from 211 –1, 215 –1 or220 –1, may  
be detected in the T1 stream in either the ingress or egress directions. The  
detector counts pattern errors using a 24-bit non-saturating PRBS error  
counter. The pseudo-random sequence can be the entire T1 or any  
combination of DS0s within a framed T1.  
Sꢀ Line side interface is the DS3 interface via the M13 multiplex.  
Sꢀ System side interface is either serial clock and data, H-MVIP or SBI bus.  
Sꢀ Frames in the presence of and detects the “Japanese Yellow” alarm.  
Sꢀ Provides external access for up to two de-jittered recovered T1 clocks.  
Each one of 21 E1 receiver sections:  
Sꢀ Frames to ITU-T G.704 basic and CRC-4 multiframe formatted E1 signals.  
The framing procedures are consistent ITU-T G.706 specifications.  
Sꢀ Provides an HDLC interface with 128 bytes of buffering for terminating the  
national use bit data link.  
PROPRIETARY AND CONFIDENTIAL  
3
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