欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM4328-PI的Datasheet PDF文件第10页浏览型号PM4328-PI的Datasheet PDF文件第11页浏览型号PM4328-PI的Datasheet PDF文件第12页浏览型号PM4328-PI的Datasheet PDF文件第13页浏览型号PM4328-PI的Datasheet PDF文件第15页浏览型号PM4328-PI的Datasheet PDF文件第16页浏览型号PM4328-PI的Datasheet PDF文件第17页浏览型号PM4328-PI的Datasheet PDF文件第18页  
STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
1
FEATURES  
Sꢀ Integrates 28 T1 framers, 21 E1 framers and a full featured M13 multiplexer  
with DS3 framer in a single monolithic device for terminating DS3 multiplexed  
T1 or E1 streams.  
Sꢀ Four fundamental modes of operation:  
Sꢀ Up to 28 T1 streams M13 multiplexed into a serial DS3.  
Sꢀ Up to 21 E1 streams multiplexed into a DS3 following the ITU-T G.747  
recommendation. This E1 mode of operation is restricted to using the  
serial clock and data or H-MVIP system interfaces.  
Sꢀ DS3 M13 Multiplexer with ingress or egress per link monitoring.  
Sꢀ Unchannelized DS3 framer mode for access to the entire DS3 payload.  
Sꢀ Supports transfer of PCM data to/from 1.544MHz and 2.048MHz serial  
interface system-side devices. Also supports a fractional T1 or E1 system  
interface with independent ingress/egress Nx64Kb/s rates. Supports a 2.048  
MHz system-side interface for T1 mode without external clock gapping.  
Sꢀ Supports 8Mb/s H-MVIP on the system interface for all T1 or E1 links, a  
separate 8Mb/s H-MVIP system interface for all T1 or E1 CAS channels and  
a separate 8Mb/s H-MVIP system interface for all T1 or E1 CCS and  
V5.1/V5.2 channels.  
Sꢀ Supports a byte serial Scaleable Bandwidth Interconnect (SBI) bus interface  
for high density system side device interconnection of up to 84 T1 streams or  
3 DS3 streams.  
Sꢀ Provides jitter attenuation in the T1 or E1 receive and transmit directions.  
Sꢀ Provides two independent de-jittered T1 or E1 recovered clocks for system  
timing and redundancy.  
Sꢀ Provides per-DS0 line loopback and per link diagnostic and line loopbacks.  
Sꢀ Provides an on-board programmable binary sequence generator and detector  
for error testing at DS3 rates. Includes support for patterns recommended in  
ITU-T O.151.  
PROPRIETARY AND CONFIDENTIAL  
1