STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
TABLE 31: MICROPROCESSOR INTERFACE WRITE ACCESS ..................204
TABLE 32: RTSB TIMING ...............................................................................206
TABLE 33: DS3 TRANSMIT INTERFACE TIMING..........................................206
TABLE 34: DS3 RECEIVE INTERFACE TIMING............................................210
TABLE 35: SBI ADD BUS TIMING (FIGURE 84) ............................................213
TABLE 36: SBI DROP BUS TIMING (FIGURE 85 TO FIGURE 86) ................214
TABLE 37: H-MVIP EGRESS TIMING (FIGURE 87).......................................217
TABLE 38: H-MVIP INGRESS TIMING (FIGURE 88) .....................................218
TABLE 39: XCLK INPUT (FIGURE 89) ...........................................................220
TABLE 40: EGRESS INTERFACE TIMING - CLOCK SLAVE: EFP ENABLED
MODE (FIGURE 90) ....................................................................221
TABLE 41: EGRESS INTERFACE TIMING - CLOCK SLAVE: EXTERNAL
SIGNALING (FIGURE 91) ...........................................................222
TABLE 42: EGRESS INTERFACE INPUT TIMING - CLOCK MASTER :
NXCHANNEL MODE (FIGURE 92) .............................................223
TABLE 43: EGRESS INTERFACE INPUT TIMING - CLOCK MASTER : CLEAR
CHANNEL MODE (FIGURE 92) ..................................................224
TABLE 44: EGRESS INTERFACE INPUT TIMING - CLOCK MASTER : SERIAL
DATAAND H-MVIP CCS MODE (FIGURE 92)............................225
TABLE 45: EGRESS INTERFACE INPUT TIMING - CLOCK SLAVE : CLEAR
CHANNEL MODE (FIGURE 92) ..................................................226
TABLE 46: INGRESS INTERFACE TIMING - CLOCK SLAVE MODES (FIGURE
96)................................................................................................227
TABLE 47: INGRESS INTERFACE TIMING - CLOCK MASTER MODES
(FIGURE 97)................................................................................229
TABLE 48: TRANSMIT LINE INTERFACE TIMING (FIGURE 98)...................230
TABLE 49: JTAG PORT INTERFACE .............................................................232
PROPRIETARY AND CONFIDENTIAL
xi
PMC [ PMC-SIERRA, INC ]
