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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
Sꢀ Extracts 4-bit codewords from the E1 national use bits as specified in  
ETS 300 233.  
Sꢀ V5.2 link indication signal detection.  
Sꢀ Provides performance monitoring counters sufficiently large as to allow  
performance monitor counter polling at a minimum rate of once per second.  
Optionally, updates the performance monitoring counters and interrupts the  
microprocessor once per second, timed to the receive line.  
Sꢀ Provides a two-frame elastic store buffer for backplane rate adaptation that  
performs controlled slips and indicates slip occurrence and direction.  
Sꢀ Frames to the E1 signaling multiframe alignment when enabled and extracts  
channel associated signaling. Alternatively, a common channel signaling data  
link may be extracted from timeslot 16.  
Sꢀ Can be programmed to generate an interrupt on change of signaling state.  
Sꢀ Provides trunk conditioning which forces programmable trouble code  
substitution and signaling conditioning on all channels or on selected  
channels.  
Sꢀ A pseudo-random sequence user selectable from 211 –1, 215 –1 or220 –1, may  
be detected in the E1 stream in either the ingress or egress directions. The  
detector counts pattern errors using a 24-bit non-saturating PRBS error  
counter. The pseudo-random sequence can be the entire E1 or any  
combination of timeslots within the framed E1.  
Sꢀ Line side interface is the DS3 interface mutiplexed as per the G.747  
recommendation.  
Sꢀ System side interface is either serial clock and data or H-MVIP.  
Sꢀ Provides external access for up to two de-jittered recovered E1 clocks.  
Each one of 28 T1 transmitter sections:  
Sꢀ May be timed to its associated receive clock (loop timing) or may derive its  
timing from a common egress clock or a common transmit clock; the transmit  
line clock may be synthesized from an N*8kHz reference.  
Sꢀ Provides minimum ones density through Bell (bit 7), GTE or “jammed bit 8”  
zero code suppression on a per-DS0 basis.  
PROPRIETARY AND CONFIDENTIAL  
4
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