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PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
Sꢀ A pseudo-random sequence user selectable from 211 –1, 215 –1 or 220 –1,  
may be inserted into the E1 stream in either the ingress or egress directions.  
The pseudo-random sequence can be inserted into the entire E1 or any  
combination of timeslots within the framed E1.  
Sꢀ Optionally inserts a datalink in the E1 national use bits.  
Sꢀ Supports 4-bit codeword insertion in the E1 national use bits as specified in  
ETS 300 233  
Sꢀ Supports transmission of the alarm indication signal (AIS) and the Yellow  
alarm signal.  
Sꢀ Line side interface is the DS3 interface mutiplexed as per the G.747  
recommendation.  
Sꢀ System side interface is either serial clock and data or H-MVIP  
DS3 Receiver Section:  
Sꢀ Frames to a DS3 signal with a maximum average reframe time of less than  
1.5 ms (as required by TR-TSY-000009 Section 4.1.2 and TR-TSY-000191  
Section 5.2).  
Sꢀ Decodes a B3ZS-encoded signal and indicates line code violations. The  
definition of line code violation is software selectable.  
Sꢀ Provides indication of M-frame boundaries from which M-subframe  
boundaries and overhead bit positions in the DS3 stream can be determined  
by external processing.  
Sꢀ Detects the DS3 alarm indication signal (AIS) and idle signal. Detection  
-3  
algorithms operate correctly in the presence of a 10 bit error rate.  
Sꢀ Extracts valid X-bits and indicates far end receive failure (FERF).  
Sꢀ Accumulates up to 65,535 line code violation (LCV) events per second,  
65,535 P-bit parity error events per second, 1023 F-bit or M-bit (framing bit)  
events per second, 65,535 excessive zero (EXZ) events per second, and  
when enabled for C-bit parity mode operation, up to 16,383 C-bit parity error  
events per second, and 16,383 far end block error (FEBE) events per  
second.  
PROPRIETARY AND CONFIDENTIAL  
6
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