STANDARD PRODUCT
PM4328 TECT3
DATASHEET
PMC-2011596
ISSUE 1
HIGH DENSITY T1/E1 FRAMER
AND M13 MULTIPLEXER
FIGURE 70: T1 AND E1 EGRESS INTERFACE CLOCK SLAVE: CLEAR
CHANNEL MODE........................................................................194
FIGURE 71: T1 INGRESS INTERFACE CLOCK MASTER : FULL CHANNEL
MODE..........................................................................................195
FIGURE 72: E1 INGRESS INTERFACE CLOCK MASTER : FULL CHANNEL
MODE..........................................................................................195
FIGURE 73: T1 INGRESS INTERFACE CLOCK MASTER: NXCHANNEL MODE196
FIGURE 74: E1 INGRESS INTERFACE CLOCK MASTER: NXCHANNEL MODE196
FIGURE 75: T1 AND E1 INGRESS INTERFACE CLOCK MASTER: CLEAR
CHANNEL MODE........................................................................196
FIGURE 76: T1 INGRESS INTERFACE CLOCK SLAVE: EXTERNAL
SIGNALING MODE......................................................................197
FIGURE 77: E1 INGRESS INTERFACE CLOCK SLAVE: EXTERNAL
SIGNALING MODE......................................................................197
FIGURE 78: T1 INGRESS INTERFACE 2.048 MHZ CLOCK SLAVE: EXTERNAL
SIGNALING MODE......................................................................198
FIGURE 79: MICROPROCESSOR INTERFACE READ TIMING....................203
FIGURE 80: MICROPROCESSOR INTERFACE WRITE TIMING..................205
FIGURE 81: RSTB TIMING.............................................................................206
FIGURE 82: DS3 TRANSMIT INTERFACE TIMING .......................................208
FIGURE 83: DS3 RECEIVE INTERFACE TIMING..........................................211
FIGURE 84: SBI ADD BUS TIMING................................................................214
FIGURE 85: SBI DROP BUS TIMING.............................................................216
FIGURE 86: SBI DROP BUS COLLISION AVOIDANCE TIMING ...................216
FIGURE 87: H-MVIP EGRESS DATA & FRAME PULSE TIMING...................218
FIGURE 88: H-MVIP INGRESS DATA TIMING...............................................219
FIGURE 89: XCLK INPUT TIMING .................................................................220
PROPRIETARY AND CONFIDENTIAL
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