欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM4328-PI 参数 Datasheet PDF下载

PM4328-PI图片预览
型号: PM4328-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度T1 / E1成帧器,集成M13多路复用器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信集成电路电信电路异步传输模式ATM
文件页数/大小: 250 页 / 1399 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM4328-PI的Datasheet PDF文件第5页浏览型号PM4328-PI的Datasheet PDF文件第6页浏览型号PM4328-PI的Datasheet PDF文件第7页浏览型号PM4328-PI的Datasheet PDF文件第8页浏览型号PM4328-PI的Datasheet PDF文件第10页浏览型号PM4328-PI的Datasheet PDF文件第11页浏览型号PM4328-PI的Datasheet PDF文件第12页浏览型号PM4328-PI的Datasheet PDF文件第13页  
STANDARD PRODUCT  
PM4328 TECT3  
DATASHEET  
PMC-2011596  
ISSUE 1  
HIGH DENSITY T1/E1 FRAMER  
AND M13 MULTIPLEXER  
FIGURE 70: T1 AND E1 EGRESS INTERFACE CLOCK SLAVE: CLEAR  
CHANNEL MODE........................................................................194  
FIGURE 71: T1 INGRESS INTERFACE CLOCK MASTER : FULL CHANNEL  
MODE..........................................................................................195  
FIGURE 72: E1 INGRESS INTERFACE CLOCK MASTER : FULL CHANNEL  
MODE..........................................................................................195  
FIGURE 73: T1 INGRESS INTERFACE CLOCK MASTER: NXCHANNEL MODE196  
FIGURE 74: E1 INGRESS INTERFACE CLOCK MASTER: NXCHANNEL MODE196  
FIGURE 75: T1 AND E1 INGRESS INTERFACE CLOCK MASTER: CLEAR  
CHANNEL MODE........................................................................196  
FIGURE 76: T1 INGRESS INTERFACE CLOCK SLAVE: EXTERNAL  
SIGNALING MODE......................................................................197  
FIGURE 77: E1 INGRESS INTERFACE CLOCK SLAVE: EXTERNAL  
SIGNALING MODE......................................................................197  
FIGURE 78: T1 INGRESS INTERFACE 2.048 MHZ CLOCK SLAVE: EXTERNAL  
SIGNALING MODE......................................................................198  
FIGURE 79: MICROPROCESSOR INTERFACE READ TIMING....................203  
FIGURE 80: MICROPROCESSOR INTERFACE WRITE TIMING..................205  
FIGURE 81: RSTB TIMING.............................................................................206  
FIGURE 82: DS3 TRANSMIT INTERFACE TIMING .......................................208  
FIGURE 83: DS3 RECEIVE INTERFACE TIMING..........................................211  
FIGURE 84: SBI ADD BUS TIMING................................................................214  
FIGURE 85: SBI DROP BUS TIMING.............................................................216  
FIGURE 86: SBI DROP BUS COLLISION AVOIDANCE TIMING ...................216  
FIGURE 87: H-MVIP EGRESS DATA & FRAME PULSE TIMING...................218  
FIGURE 88: H-MVIP INGRESS DATA TIMING...............................................219  
FIGURE 89: XCLK INPUT TIMING .................................................................220  
PROPRIETARY AND CONFIDENTIAL  
viii  
 复制成功!