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PM4318 参数 Datasheet PDF下载

PM4318图片预览
型号: PM4318
PDF下载: 下载PDF文件 查看货源
内容描述: 八进制E1 / T1 / J1线路接口设备 [OCTAL E1/T1/J1 LINE INTERFACE DEVICE]
分类和应用:
文件页数/大小: 244 页 / 2135 K
品牌: PMC [ PMC-SIERRA, INC ]
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PRELIMINARY  
PM4318 OCTLIU  
DATASHEET  
PMC- 2001578  
ISSUE 3  
OCTAL E1/T1/J1 LINE INTERFACE DEVICE  
Register 009H, 089H, 109H, 189H, 209H, 289H, 309H, 389H:  
Receive Line Interface Configuration #2  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R/W  
RJATBYP  
Unused  
1
X
X
X
X
0
Unused  
Unused  
Unused  
R/W  
R/W  
R/W  
RSYNC_ALOSB  
RSYNC_MEM  
RSYNCSEL  
0
0
RJATBYP:  
The RJATBYP bit disables jitter attenuation in the receive direction. When receive jitter  
attenuation is not being used, setting RJATBYP to logic 1 will reduce the latency through the  
receiver section by typically 40 bits. When RJATBYP is set to logic 0, the LIU’s RSYNC  
output is jitter attenuated. When the RJAT is bypassed, the octant’s RSYNC is not jitter  
attenuated.  
RSYNC_ALOSB:  
The RSYNC_ALOSB bit controls the source of the loss of signal condition used to control the  
behaviour of the receive reference presented on the RSYNC output. If RSYNC_ALOSB is a  
logic 0, analogue loss of signal is used. If RSYNC_ALOSB is a logic 1, digital loss of signal is  
used. When the LIU is in a loss of signal state, the RSYNC output is derived from XCLK or  
held high, as determined by the RSYNC_MEM bit. When the LIU is not in a loss of signal  
state, the RSYNC output is derived from the receive recovered clock of the selected octant.  
The octant to be used as the source of RSYNC is determined by the RSYNC_SEL[2:0] bits.  
RSYNC_MEM:  
The RSYNC_MEM bit controls the octant’s RSYNC output under a loss of signal condition (as  
determined by the RSYNC_ALOSB register bit). When RSYNC_MEM is a logic 1, the  
octant’s RSYNC output is held high during a loss of signal condition. When RSYNC_MEM is  
a logic 0, the octant’s RSYNC output is derived from the CSU 1x line rate clock during a loss  
of signal condition.  
RSYNCSEL:  
The RSYNCSEL bit selects the frequency of the receive reference presented on the octant’s  
RSYNC output. If RSYNCSEL is a logic 1, the octant’s RSYNC will be an 8 kHz clock. If  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
69  
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