PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
logic 1, the digital outputs of the CSU are pulled to ground. When either the IDDQ_EN bit or
IDDQEN bit is set to logic 1, the HIGHZ bit in the XLPG Line Driver Configuration register
must also be set to logic 1.
CSU_RESET:
Setting the CSU_RESET bit to logic 1 causes the embedded CSU to be forced to a frequency
much lower than normal operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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