PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
is output on RDP[n] (decoded according to AMI, B8ZS or HDB3) and line code violations /
excessive zeros are signalled on RLCV[n].
If RDUAL is set to logic 1, the PDVD, IBCD and PRBS blocks, and also the ability to generate
AIS, are disabled in the LIU receive path.
BPV:
In T1 mode, the BPV bit enables only bipolar violations to indicate line code violations and be
accumulated in the PMON LCV Count Registers. When BPV is set to logic 1, BPVs
(provided they are not part of a valid B8ZS signature if B8ZS line coding is used) generate an
LCV indication and increment the PMON LCV counter. When BPV is set to logic 0, both
BPVs (provided they are not part of a valid B8ZS signature if B8ZS line coding is used) and
excessive zeros (EXZ) generate an LCV indication and increment the PMON LCV counter.
Excessive zeros is a sequence of zeros greater than fifteen bits long for an AMI-coded signal
and greater than seven bits long for a B8ZS-coded signal.
In E1 mode, the BPV bit enables only bipolar violations to indicate line code violations and be
accumulated in the PMON LCV Count Registers. (The O162 bit in the CDRC Configuration
register provides two E1 LCV definitions.) When BPV is set to logic 1, BPVs (provided they
are not part of a valid HDB3 signature if HDB3 line coding is used) generate an LCV
indication and increment the PMON LCV counter. When BPV is set to logic 0, both BPVs
(provided they are not part of a valid HDB3 signature if HDB3 line coding is used) and
excessive zeros (EXZ) generate an LCV indication and increment the PMON LCV counter.
Excessive zeros is a sequence of zeros greater than fifteen bits long for an AMI-coded signal
and greater than four bits long for an HDB3-coded signal.
RINV:
When RINV is set to logic 1, the receive digital outputs RDP[n] and RDN/RLCV[n] are
assumed to be active low and all output data and LCV indications are inverted. When RINV
is set to logic 0, the receive digital outputs RDP[n] and RDN/RLCV[n] are assumed to be
active high. RINV must be set to 0 when the SBI interface is enabled (SBI_EN = 1).
RFALL:
When RFALL is set to logic 1, the RDP[n] and RDN/RLCV[n] outputs are updated on falling
edges of RCLK[n]. When RFALL is set to logic 0, the outputs are updated on rising edges of
RCLK[n]. RFALL must be set to 1 when the SBI interface is enabled (SBI_EN = 1).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
68
PMC [ PMC-SIERRA, INC ]
