PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 006H: CSU Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
CSU_RESET
IDDQ_EN
Unused
0
0
X
X
X
0
0
0
Unused
R
CSU_LOCK
MODE[2]
MODE[1]
MODE[0]
R/W
R/W
R/W
MODE[2:0]:
The MODE[2:0] selects the mode of the CSU. Table 5 indicates the required XCLK
frequency, and output frequencies for each mode.
Table 5
– Clock Synthesis Mode
MODE[2:0]
XCLK frequency
Transmit clock
frequency
000
001
01X
10X
110
111
2.048 MHz
1.544 MHz
Reserved
Reserved
Reserved
2.048 MHz
2.048 MHz
1.544 MHz
Reserved
Reserved
Reserved
1.544 MHz
CSU_LOCK:
The CSU_LOCK bit can be used to determine whether or not the embedded clock synthesis
unit (CSU) has achieved phase and frequency lock to XCLK. If the CSU_LOCK bit is polled
repetitively and is persistently a logic 1, then the divided down synthesized clock frequency is
within 244 ppm of the XCLK frequency. A persistent logic 0 may indicate a mismatch
between the actual and expected XCLK frequency or a problem with the analogue supplies
(CAVS and CAVD).
IDDQ_EN:
The IDDQ enable bit (IDDQ_EN) is used to configure the embedded CSU for IDDQ tests.
When IDDQ_EN is a logic 1, or the IDDQEN bit in the Master Test Control #1 register is a
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65
PMC [ PMC-SIERRA, INC ]
