PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 004H: Master Test Control #1
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
W
W
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
HIZDATA
HIZIO
X
X
X
X
0
0
0
0
W
W
W
R/W
W
R/W
This register is used to select OCTLIU test features. All bits, except for 7,6,5 and 4 are reset to
zero by a hardware reset of the OCTLIU, a software reset of the OCTLIU does not affect the state
of the bits in this register.
HIZIO, HIZDATA:
The HIZIO and HIZDATA bits control the tri-state modes of the OCTLIU. While the HIZIO bit
is a logic 1, all output pins of the OCTLIU except TDO and the data bus are held in a high-
impedance state. The microprocessor interface is still active. While the HIZDATA bit is a
logic 1, the data bus is held in a high-impedance state which inhibits microprocessor read
cycles.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
63
PMC [ PMC-SIERRA, INC ]
