PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
The SBI multiplexing structure is modeled on the SONET/SDH standards. The SONET/SDH
virtual tributary structure is used to carry T1/J1 and E1 links. Unchannelized DS3 payloads (not
used by OCTLIU) follow a byte synchronous structure modeled on the SONET/SDH format.
The SBI structure uses a locked SONET/SDH structure fixing the position of the TUG-3/TU-3
relative to the STS-3/STM-1 transport frame. The SBI is also of fixed frequency and alignment as
determined by the reference clock (REFCLK) and frame indicator signal (C1FP). Frequency
deviations are compensated by adjusting the location of the T1/J1/E1/DS3 channels using
floating tributaries as determined by the V5 indicator and payload signals (DV5, AV5, DPL and
APL). Note that the OCTLIU always operates as a clock slave on the SBI ADD bus and as a
clock master on the SBI DROP bus, i.e. it does not support the AJUST_REQ and DJUST_REQ
timing adjustment request signals defined in the SBI bus specification.
The multiplexed links are separated into three Synchronous Payload Envelopes (SPE). Each
envelope may be configured independently to carry up to 28 T1/J1s, 21 E1s or a DS3. The
OCTLIU may be configured to use any eight T1/J1 tributaries or any eight E1 tributaries from any
of the three SPE’s. The eight tributaries need not all be selected from the same SPE. A single
OCTLIU device cannot, however, use T1/J1 and E1 tributaries simultaneously.
9.14.1
Interfacing OCTLIUs to a High Density Framer
Figure 14 – SBI to Framer Line Side Interface
19.44MHz
LREFCLK
LAC1
REFCLK
C1FPOUT
AC1FP
ADATA[7:0]
ADP
LAC1J1V1
LADATA[7:0]
LADP
LATPL
APL
LAV5
AV5
LAPL
LDC1J1V1
LDDATA[7:0]
LDDP
DC1FP
DDATA[7:0]
DDP
LDTPL
DPL
LDV5
DV5
LDPL
LDAIS
Framer
OCTLIUs
Figure 14 shows how the SBI interfaces of multiple OCTLIU’s may be connected to the line side
interface of a high density framer. With the exception of C1FPOUT, all signals on the OCTLIU
side are simply bussed in parallel to the multiple devices. The C1FPOUT port of a single OCTLIU
is used to provide a frame reference for all the devices. Alternatively, the C1 frame pulse can be
generated by external circuitry if desired. The framer’s interface must be configured such that VT
pointer processors are bypassed, VT’s are byte synchronously mapped, and that the STS-1
SPE’s are locked to the STS-3 transport envelope with a fixed pointer offset of 522.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
45
PMC [ PMC-SIERRA, INC ]
