PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
9.12 Line Transmitter
The line transmitter generates Alternate Mark Inversion (AMI) transmit pulses suitable for use in
the DSX-1 (short haul T1), short haul E1, long haul T1 and long haul E1 environments. The
voltage pulses are produced by applying a current to a known termination (termination resistor
plus line impedance). The use of current (instead of a voltage driver) simplifies transmit Input
Return Loss (IRL), transmit short circuit protection (none needed) and transmit tri-stating.
The output pulse shape is synthesized digitally with current digital-to-analogue (DAC) converters,
which produce 24 samples per symbol. The current DAC’s produce differential bipolar outputs
that directly drive the TXTIP1[x], TXTIP2[x], TXRING1[x] and TXRING2[x] pins. The current
output is applied to a terminating resistor and line-coupling transformer in a differential manner,
which when viewed from the line side of the transformer produce the output pulses at the required
levels and ensures a small positive to negative pulse imbalance.
The pulse shape is user programmable. For T1 short haul, the cable length between the OCTLIU
and the cross-connect (where the pulse template specifications are given) greatly affects the
resulting pulse shapes. Hence, the data applied to the converter must account for different cable
lengths. For CEPT E1 applications the pulse template is specified at the transmitter, thus only
one setting is required. For T1 long haul with a LBO of 7.5 dB the previous bits effect what the
transmitter must drive to compensate for inter-symbol interference; for LBO’s of 15 dB or 22.5 dB
the previous 3 or 4 bits effect what the transmitter must send out.
Refer to the Operation section for details on creating the synthesized pulse shape.
9.13 Timing Options (TOPS)
The Timing Options block provides a means of selecting the source of the internal input clock to
the TJAT block, and the reference clock for the TJAT digital PLL.
9.14 Scaleable Bandwidth Interconnect (SBI) Interface
The Scaleable Bandwidth Interconnect is a synchronous, time-division multiplexed bus designed
to transfer, in a pin-efficient manner, data belonging to a number of independently timed links of
varying bandwidth. The bus is timed to a reference 19.44MHz clock and a 2 kHz (or fraction
thereof) frame pulse. All sources and sinks of data on the bus are timed to the reference clock
and frame pulse.
Timing is communicated across the Scaleable Bandwidth Interconnect by floating data structures.
Payload indicator signals in the SBI control the position of the floating data structure and
therefore the timing. When sources are running faster than the SBI the floating payload structure
is advanced by an octet by passing an extra octet in the V3 octet locations (H3 octet for DS3
mappings which are not used by the OCTLIU). When the source is slower than the SBI the
floating payload is retarded by leaving the octet after the V3 or H3 octet unused. Both these rate
adjustments are indicated by the SBI control signals.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
44
PMC [ PMC-SIERRA, INC ]
