PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
dominated by the generated residual jitter in cases where incoming jitter is insignificant. This
generated residual jitter is directly related to the use of a 1/96 UI phase adjustment quantum.
TJAT meets the jitter attenuation requirements of AT&T TR 62411. The block allows the implied
jitter attenuation requirements for a TE or NT1 given in ANSI Standard T1.408, and the implied
jitter attenuation requirements for a type II customer interface given in ANSI T1.403 to be met.
Jitter Tolerance
Jitter tolerance is the maximum input phase jitter at a given jitter frequency that a device can
accept without exceeding its linear operating range, or corrupting data. For TJAT, the input jitter
tolerance is 61 Unit Intervals peak-to-peak (Uipp) with a worst case frequency offset of 354 Hz. It
is 80 Uipp with no frequency offset. The frequency offset is the difference between the frequency
of XCLK and that of the input data clock.
Figure 11 – TJAT Jitter Tolerance
100
61
JAT
28
MIN.TOLER
ANCE
10
JITTER
AMPLITUDE,
UI pp
1.0
acceptable
0.4
unacceptable
0.1
0.01
10
1
100
JITTER FREQUENCY, Hz
1k
10k
100k
The accuracy of the XCLK frequency and that of the TJAT PLL reference input clock used to
generate the jitter-free Transmit clock output have an effect on the minimum jitter tolerance.
Given that the TJAT PLL reference clock accuracy can be ±200 Hz and that the XCLK input
accuracy can be ±100 ppm, the minimum jitter tolerance for various differences between the
frequency of PLL reference clock and XCLK are shown in Figure 12.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
41
PMC [ PMC-SIERRA, INC ]
