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PM4318 参数 Datasheet PDF下载

PM4318图片预览
型号: PM4318
PDF下载: 下载PDF文件 查看货源
内容描述: 八进制E1 / T1 / J1线路接口设备 [OCTAL E1/T1/J1 LINE INTERFACE DEVICE]
分类和应用:
文件页数/大小: 244 页 / 2135 K
品牌: PMC [ PMC-SIERRA, INC ]
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PRELIMINARY  
PM4318 OCTLIU  
DATASHEET  
PMC- 2001578  
ISSUE 3  
OCTAL E1/T1/J1 LINE INTERFACE DEVICE  
Reg[13:0]  
3FFE  
Action  
Pause for Data[7:0] x 4096 XCLK periods before reading next PROM  
command.  
3FFF  
Stop, i.e. configuration of OCTLIU has finished.  
The ‘ignore subsequent register write commands’ command can be used to configure multiple  
OCTLIU’s in a cascade individually (for example, to allocate different SBI tributaries to different  
OCTLIU devices). It provides a means to progressively ‘switch off’ each device in the cascade  
once it has been configured. Consider for example the following sequence of configuration  
commands:  
Command  
(hex)  
Explanation  
C00102  
Write 02 to register 01 of all devices in the cascade, regardless of SRCODE.  
:
:
(Subsequent configuration commands are acted upon by all devices in the  
cascade.)  
3FFD00  
First device in cascade ignores all further register writes.  
C00103  
:
Write 03 to register 01 of all devices in the cascade except the first,  
regardless of SRCODE.  
:
:
(Subsequent configuration commands are acted upon by all devices in the  
cascade except the first.)  
3FFD00  
Second device in cascade ignores all further register writes.  
C00104  
:
Write 04 to register 01 of all devices in the cascade except the first two,  
regardless of SRCODE.  
:
:
(Subsequent configuration commands are acted upon by all devices in the  
cascade except the first and second.)  
The pause command can be used, for example, to allow the clock synthesis circuitry within the  
CSD block time to stablise before configuring the rest of the device.  
9.19 JTAG Test Access Port  
The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG  
EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported.  
9.20 Microprocessor Interface  
The Microprocessor Interface Block provides normal and test mode registers, the interrupt logic,  
and the logic required to connect to the Microprocessor Interface. The normal mode registers are  
required for normal operation, and test mode registers are used to enhance the testability of the  
OCTLIU.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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