PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
This block monitors the digital output of the transmitter and detects when the stream is about to
violate the ANSI T1.403 12.5% pulse density rule over a moving 192-bit window. If a density
violation is detected, the block can be enabled to insert a logic 1 into the digital stream to ensure
the resultant output no longer violates the pulse density requirement. When the XPDE is disabled
from inserting logic 1s, the digital stream from the transmitter is passed through unaltered.
9.11 Transmit Jitter Attenuator (TJAT)
The Transmit Jitter Attenuation function is provided by a digital phase lock loop and 80-bit deep
FIFO. The TJAT receives jittery, dual-rail data in NRZ format on two separate inputs, which
allows bipolar violations to pass through the block uncorrected. The incoming data streams are
stored in a FIFO timed to the transmit clock. The respective input data emerges from the FIFO
timed to the jitter attenuated clock.
The jitter attenuator generates the jitter-free 1.544 MHz or 2.048 MHz Transmit clock output by
adjusting the Transmit clock’s phase in 1/96 UI increments to minimize the phase difference
between the generated Transmit clock and input data clock to TJAT. Jitter fluctuations in the
phase of the input data clock are attenuated by the phase-locked loop within TJAT so that the
frequency of Transmit clock is equal to the average frequency of the input data clock. For T1
applications, to best fit the jitter attenuation transfer function recommended by TR 62411, phase
fluctuations with a jitter frequency above 5.7 Hz are attenuated by 6 dB per octave of jitter
frequency. Wandering phase fluctuations with frequencies below 5.7 Hz are tracked by the
generated Transmit clock. In E1 applications, the corner frequency is 7.6 Hz. To provide a
smooth flow of data out of TJAT, the Transmit clock is used to read data out of the FIFO.
If the FIFO read pointer (timed to the Transmit clock) comes within one bit of the write pointer
(timed to the input data clock), TJAT will track the jitter of the input clock. This permits the phase
jitter to pass through unattenuated, inhibiting the loss of data.
Jitter Characteristics
The TJAT Block provides excellent jitter tolerance and jitter attenuation while generating minimal
residual jitter. It can accommodate up to 61 Uipp of input jitter at jitter frequencies above 5.7 Hz
(7.6 Hz for E1). For jitter frequencies below 5.7 Hz (7.6 Hz for E1), more correctly called wander,
the tolerance increases 20 dB per decade. In most applications the TJAT Block will limit jitter
tolerance at lower jitter frequencies only. For high frequency jitter, above 10 kHz for example,
other factors such as clock and data recovery circuitry may limit jitter tolerance and must be
considered. For low frequency wander, below 10 Hz for example, other factors such as slip buffer
hysteresis may limit wander tolerance and must be considered. The TJAT block meets the
stringent low frequency jitter tolerance requirements of AT&T TR 62411 and thus allows
compliance with this standard and the other less stringent jitter tolerance standards cited in the
references.
TJAT exhibits negligible jitter gain for jitter frequencies below 5.7 Hz (7.6 Hz for E1), and
attenuates jitter at frequencies above 5.7 Hz (7.6 Hz for E1) by 20 dB per decade. In most
applications, the TJAT block will determine jitter attenuation for higher jitter frequencies only.
Wander, below 10 Hz for example, will essentially be passed unattenuated through TJAT. Jitter,
above 10 Hz for example, will be attenuated as specified, however, outgoing jitter may be
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
40
PMC [ PMC-SIERRA, INC ]
