PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
defined as a BPV that is not part of a zero substitution code for B8ZS-coded signals, and is
defined as a bipolar violation of the same polarity as the last bipolar violation for HDB3-coded
signals.
In T1 mode, the input jitter tolerance of the OCTLIU complies with the Bellcore Document
TA-TSY-000170 and with the AT&T specification TR62411, as shown in Figure 9. The tolerance is
20
measured with a QRSS sequence (2 -1 with 14 zero restriction). The CDRC block provides two
algorithms for clock recovery that result in differing jitter tolerance characteristics. The first
algorithm (when the ALGSEL register bit is logic 0) provides good low frequency jitter tolerance,
but the high frequency tolerance is close to the TR62411 limit. The second algorithm (when
ALGSEL is logic 1) provides much better high frequency jitter tolerance at the expense of the low
frequency tolerance; the low frequency tolerance of the second algorithm is approximately 80%
that of the first algorithm.
Figure 9 – T1 Jitter Tolerance
10
Acceptable Range
Sine W ave
Jitter
Amplitude
P. to P. (UI)
Log Scale
1.0
Bellcore Spec.
AT&T Spec.
0.3
0.2
0.1
0.1
0.30 0.31
1.0
10
100
Sine W ave Jitter Frequency (kHz) Log Scale
For E1 applications, the input jitter tolerance complies with the ITU-T Recommendation G.823
“The Control of Jitter and Wander Within Digital Networks Which are Based on the 2048 kbit/s
Hierarchy.” Figure 10 illustrates this specification and the performance of the phase-locked loop
when the ALGSEL register bit is logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
37
PMC [ PMC-SIERRA, INC ]
