PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Figure 8 gives the recommended external protection circuitry for designs required to meet the
major surge immunity and electrical safety standards including FCC Part 68, UL1950, and
Bellcore TR-NWT-001089. This circuit has not been tested as of December, 1999. Please refer to
an upcoming PMC application note for more details.
For systems not requiring phantom feed or inter-building line protection, the Bi-directional
Transient Surge Suppressors (Z1-Z4), their associated ground connection and the center tap of
the transformer can be removed from the circuit.
See Table 1 for the descriptions of components for Figure 8.
Note that the crowbar devices (Z1 – Z4) are not required if the transformer’s isolation rating is not
exceeded.
Table 1
Component
R1
– External Component Descriptions
Description
Part #
Source
36.0Ω 1%, 0.25W Resistor
27.0Ω 1%, 0.25W Resistor
Surge Protector Diode Array
R2
D1
SRDA3.3-4
Semtech
Pulse
T1 & T2
1:1.58 CT Transformers (E1 75Ω cable)
1:2 CT Transformers (otherwise)
Z1 – Z4
Z5 – Z6
L1 & L2
F1 – F4
Bi-directional Transient Surge Suppressors
Bi-directional Transient Surge Suppressors
Dual Choke, 27µH
P1800SC
P0720SC
PE-68624
F1250T
Teccor
Teccor
Pulse
Telecom/Time Lag Fuses
Teccor
When operating in E1 mode with 75Ω cable, a 1:1.58 turns ratio transformer is specified in the
above table. It is in fact also possible to use a 1:2 turns ratio transformer, in which case the value
of R1 must be changed to 22.0Ω 1% and the value of R2 must be changed to 18.0Ω 1%.
9.3
Clock and Data Recovery (CDRC)
The Clock and Data Recovery function is provided by the Clock and Data Recovery (CDRC)
block. The CDRC provides clock and PCM data recovery, B8ZS and HDB3 decoding, line code
violation detection, and loss of signal detection. It recovers the clock from the incoming RZ data
pulses using a digital phase-locked-loop and reconstructs the NRZ data. Loss of signal is
indicated after a programmable threshold of consecutive bit periods of the absence of pulses on
both the positive and negative line pulse inputs and is cleared after the occurrence of a single line
pulse. An alternate loss of signal indication is provided which is cleared upon meeting an 1-in-8
pulse density criteria for T1 and a 1-in-4 pulse density criteria for E1. If enabled, a
microprocessor interrupt is generated when a loss of signal is detected and when the signal
returns. A line code violation is defined as a bipolar violation (BPV) for AMI-coded signals, is
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
36
PMC [ PMC-SIERRA, INC ]
