PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
7. The 3.3 Volt power pins (i.e., TAVD1, TAVD2, TAVD3, CAVD, RAVD1, RAVD2, QAVD, and
VDD3V3) will be collectively referred to as V in this document.
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should be applied before power to the VDD1V8 pins is applied. Similarly,
8. Power to V
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power to the VDD1V8 pins should be removed before power to V
is removed.
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9. The V
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voltage level should not be allowed to drop below the VDD1V8 voltage level
except when VDD1V8 is not powered.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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