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PM4318 参数 Datasheet PDF下载

PM4318图片预览
型号: PM4318
PDF下载: 下载PDF文件 查看货源
内容描述: 八进制E1 / T1 / J1线路接口设备 [OCTAL E1/T1/J1 LINE INTERFACE DEVICE]
分类和应用:
文件页数/大小: 244 页 / 2135 K
品牌: PMC [ PMC-SIERRA, INC ]
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PRELIMINARY  
PM4318 OCTLIU  
DATASHEET  
PMC- 2001578  
ISSUE 3  
OCTAL E1/T1/J1 LINE INTERFACE DEVICE  
Pin Name  
Type  
Pin  
No.  
Function  
SBI to Clk/Data Converter Interface  
SBI_EN  
SBI2CLK  
Input  
B16  
C1  
The SBI interface enable signals (SBI_EN, SBI2CLK) select  
between the SBI and serial clock/data system side interfaces and  
allow selection of an operating mode in which the LIUs are  
disabled and the OCTLIU functions as a converter between the  
SBI interface and serial clk/data. The signals select the device  
operating mode as follows:  
SBI_EN  
0
SBI2CLK  
Mode  
0
0
LIUs enabled, clk/data selected on system  
side.  
1
LIUs enabled, SBI interface selected on  
system side.  
0
1
1
1
LIUs disabled, converter mode.  
Unused  
IDATA[1]/TCLK[1]  
IDATA[2]/TCLK[2]  
IDATA[3]/TCLK[3]  
IDATA[4]/TCLK[4]  
IDATA[5]/TCLK[5]  
IDATA[6]/TCLK[6]  
IDATA[7]/TCLK[7]  
IDATA[8]/TCLK[8]  
Input  
U19  
The Ingress Data inputs (IDATA[8:1]) carry eight serial 1.544  
Mbps or 2.048 Mbps data streams to be mapped on to the SBI  
W20  
AA22 interface when the device is operating as a SBI to clk/data  
AA20 converter. The eight serial data streams are sampled on the  
W2  
V3  
U4  
V1  
rising edge of ICLK_IN.  
IDATA[8:1] share the same pins as the TCLK[8:1] inputs.  
IDATA[8:1] are selected when SBI2CLK is tied high.  
ICLK_IN/TDN[7]  
Input  
Input  
V2  
The Ingress Input Clock (ICLK_IN) should be 1.544 MHz for DS1  
or 2.048 MHz for E1 data streams and is used to sample the  
IDATA[8:1] and IFP_IN signals.  
ICLK_IN shares the same pin as the TDN[7] input. ICLK_IN is  
selected when SBI_EN or SBI2CLK is tied high.  
IFP_IN/TDN[8]  
U3  
The Ingress Frame Pulse input (IFP_IN) should be set high  
during the framing bits of DS1 streams or during the first bit of the  
framing octet of E1 data streams. IFP_IN is sampled on the  
rising edge of ICLK_IN.  
IFP_IN shares the same pin as the TDN[8] input. IFP_IN is  
selected when SBI_EN or SBI2CLK is tied high.  
ICLK_OUT/RSYNC  
Output  
D8  
The Ingress Output Clock (ICLK_OUT) is a nominal 1.544 MHz  
(for DS1) or 2.048 MHz (for E1) clock and may be used as a  
source for the ICLK_IN clock if desired.  
ICLK_OUT shares the same pin as the RSYNC output.  
ICLK_OUT is selected when SBI2CLK is tied high.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
20  
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