PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name
Type
Pin
No.
Function
ADP/TDN[4]
Input
W18
The SBI ADD bus parity signal (ADP) carries the even or odd
parity for the ADD bus signals. The parity calculation
encompasses the ADATA[7:0], APL and AV5 signals.
Multiple devices can drive the SBI ADD bus at uniquely assigned
tributary column positions. This parity signal is intended to detect
accidental driver clashes in the column assignment.
ADP is sampled on the rising edge of REFCLK.
ADP shares the same pin as the TDN[4] input. ADP is selected
when SBI_EN or SBI2CLK is tied high.
APL/TDN[5]
Input
AA1
The SBI ADD bus payload signal (APL) indicates valid data within
the SBI TDM bus structure. This signal is asserted during all
octets making up a tributary. This signal may be asserted during
the V3 octet within a tributary to accommodate negative timing
adjustments between the tributary rate and the fixed TDM bus
structure. This signal may be deasserted during the octet
following the V3 octet within a tributary to accommodate positive
timing adjustments between the tributary rate and the fixed TDM
bus structure.
APL is sampled on the rising edge of REFCLK.
APL shares the same pin as the TDN[5] input. APL is selected
when SBI_EN or SBI2CLK is tied high.
AV5/TDN[6]
Input
V4
The SBI ADD bus payload indicator signal (AV5) locates the
position of the floating payloads for each tributary within the SBI
TDM bus structure. Timing differences between the port timing
and the TDM bus timing are indicated by adjustments of this
payload indicator relative to the fixed TDM bus structure. All
movements indicated by this signal must be accompanied by
appropriate adjustments in the APL signal.
AV5 is sampled on the rising edge of REFCLK.
AV5 shares the same pin as the TDN[6] input. AV5 is selected
when SBI_EN or SBI2CLK is tied high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
16
PMC [ PMC-SIERRA, INC ]
