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PM4318 参数 Datasheet PDF下载

PM4318图片预览
型号: PM4318
PDF下载: 下载PDF文件 查看货源
内容描述: 八进制E1 / T1 / J1线路接口设备 [OCTAL E1/T1/J1 LINE INTERFACE DEVICE]
分类和应用:
文件页数/大小: 244 页 / 2135 K
品牌: PMC [ PMC-SIERRA, INC ]
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PRELIMINARY  
PM4318 OCTLIU  
DATASHEET  
PMC- 2001578  
ISSUE 3  
OCTAL E1/T1/J1 LINE INTERFACE DEVICE  
Pin Name  
Type  
Pin  
No.  
Function  
DV5/RDN/RLCV[6]  
Tristate  
output  
AB5  
The SBI DROP bus payload indicator signal (DV5) locates the  
position of the floating payloads for each tributary within the SBI  
TDM bus structure. Timing differences between the port timing  
and the TDM bus timing are indicated by adjustments of this  
payload indicator relative to the fixed TDM bus structure.  
Multiple LIU devices can drive this signal at uniquely assigned  
tributary column positions. DV5 is tristated when the OCTLIU is  
not outputting data on a particular tributary column.  
DV5 is updated on the rising edge of REFCLK.  
DV5 shares the same pin as the RDN/RLCV[6] output. DV5 is  
selected when SBI_EN or SBI2CLK is tied high.  
Output  
Y4  
The SBI DROP bus active indicator signal (DACTIVE) is asserted  
whenever the OCTLIU is driving the SBI DROP bus signals,  
DDATA[7:0], DDP, DPL and DV5.  
DACTIVE/RDN/RLCV[8]  
DACTIVE is updated on the rising edge of REFCLK.  
DACTIVE shares the same pin as the RDN/RLCV[8] output.  
DACTIVE is selected when SBI_EN or SBI2CLK is tied high.  
Transmit Line Interface  
TXTIP1[1]  
TXTIP1[2]  
TXTIP1[3]  
TXTIP1[4]  
TXTIP1[5]  
TXTIP1[6]  
TXTIP1[7]  
TXTIP1[8]  
Analogue A12  
Transmit Analogue Positive Pulse (TXTIP1[8:1] and TXTIP2[8:1]).  
When the transmit analogue line interface is enabled, the  
TXTIP1[x] and TXTIP2[x] analogue outputs drive the transmit line  
Output  
K22  
N22  
AB12 pulse signal through an external matching transformer. Both  
AB9  
L1  
H1  
A9  
TXTIP1[x] and TXTIP2[x] are normally connected to the positive  
lead of the transformer primary. Two outputs are provided for  
better signal integrity and must be shorted together on the board.  
After a reset, TXTIP1[x] and TXTIP2[x] are high impedance. The  
HIGHZ bit of the octant’s XLPG Line Driver Configuration register  
must be programmed to logic 0 to remove the high impedance  
state.  
TXTIP2[1]  
TXTIP2[2]  
TXTIP2[3]  
TXTIP2[4]  
TXTIP2[5]  
TXTIP2[6]  
TXTIP2[7]  
TXTIP2[8]  
A11  
L22  
M22  
AB11  
AB10  
K1  
J1  
A10  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
18  
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