PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name
Type
Pin
No.
Function
Output
AB18 The Ingress Frame Pulse output (IFP_OUT) is pulsed high every
193 ICLK_OUT cycles for DS1 and every 256 ICLK_OUT cycles
for E1. It may be used as a framing reference and as a source
for IFP_IN if desired. IFP_OUT is updated on the falling edge of
ICLK_OUT.
IFP_OUT/RDN/RLCV[1]
IFP_OUT shares the same pin as the RDN/RLCV[1] output.
IFP_OUT is selected when SBI_EN or SBI2CLK is tied high.
EDATA[1]/RCLK[1]
EDATA[2]/RCLK[2]
EDATA[3]/RCLK[3]
EDATA[4]/RCLK[4]
EDATA[5]/RCLK[5]
EDATA[6]/RCLK[6]
EDATA[7]/RCLK[7]
EDATA[8]/RCLK[8]
Output
AA19 The Egress Data outputs (EDATA[8:1]) carry eight serial 1.544
AA18 Mbps or 2.048 Mbps data streams de-mapped from the SBI
Y16
interface when the device is operating as a SBI to clk/data
AA15 converter. The eight serial data streams are updated on the
AB6
W7
falling edge of ECLK.
EDATA[8:1] share the same pins as the RCLK[8:1] outputs.
EDATA[8:1] are selected when SBI2CLK is tied high.
W6
AB2
ECLK/RDN/RLCV[7]
Output
Output
AA4
The Egress Clock output (ECLK) is a 1.544 MHz (for DS1) or
2.048 MHz (for E1) clock, recovered from one of the SBI
tributaries. The SBI tributary used to recover timing is selectable.
ECLK shares the same pin as the RDN/RLCV[7] output. ECLK is
selected when SBI_EN or SBI2CLK is tied high.
EFP/RDN/RLCV[2]
AB17 The Egress Frame Pulse output (EFP) is set high during the
framing bits of DS1 streams or during the first bit of the framing
octet of E1 data streams. EFP is updated on the falling edge of
ECLK.
EFP shares the same pin as the RDN/RLCV[2] output. EFP is
selected when SBI_EN or SBI2CLK is tied high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
21
PMC [ PMC-SIERRA, INC ]
