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PM4318 参数 Datasheet PDF下载

PM4318图片预览
型号: PM4318
PDF下载: 下载PDF文件 查看货源
内容描述: 八进制E1 / T1 / J1线路接口设备 [OCTAL E1/T1/J1 LINE INTERFACE DEVICE]
分类和应用:
文件页数/大小: 244 页 / 2135 K
品牌: PMC [ PMC-SIERRA, INC ]
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PRELIMINARY  
PM4318 OCTLIU  
DATASHEET  
PMC- 2001578  
ISSUE 3  
OCTAL E1/T1/J1 LINE INTERFACE DEVICE  
Pin Name  
Type  
Pin  
No.  
Function  
Microprocessor Interface  
A[0]/LEN1[0]  
A[1]/LEN1[1]  
A[2]/LEN1[2]  
A[3]/LEN2[0]  
A[4]/LEN2[1]  
A[5]/LEN2[2]  
A[6]/LEN3[0]  
A[7]/LEN3[1]  
A[8]/LEN3[2]  
A[9]/LEN4[0]  
A[10]/LEN4[1]  
Input  
E22  
E21  
E20  
F19  
D22  
D21  
D20  
E19  
C22  
C21  
C20  
Address Bus (A[10:0]). This bus selects specific registers during  
OCTLIU register accesses.  
Signal A[10] selects between normal mode and test mode register  
access. A[10] has an internal pull down resistor.  
A[10:0] share the same pins as some of the LENx[2:0] inputs.  
A[10:0] are selected when HW_ONLY is tied low.  
ALE/LEN4[2]  
Input  
A22  
Address Latch Enable (ALE). This signal is active high and  
latches the address bus contents, A[10:0], when low. When ALE  
is high, the internal address latches are transparent. ALE allows  
the OCTLIU to interface to a multiplexed address/data bus. The  
ALE input has an internal pull up resistor.  
ALE shares the same pin as the LEN4[2] input. ALE is selected  
when HW_ONLY is tied low.  
WRB/LEN5[0]  
RDB/LEN5[1]  
CSB/LEN5[2]  
Input  
Input  
Input  
D18  
C19  
B20  
Active Low Write Strobe (WRB). This signal is low during a  
OCTLIU register write access. The D[7:0] bus contents are  
clocked into the addressed register on the rising WRB edge while  
CSB is low.  
WRB shares the same pin as the LEN5[0] input. WRB is selected  
when HW_ONLY is tied low.  
Active Low Read Enable (RDB). This signal is low during  
OCTLIU register read accesses. The OCTLIU drives the D[7:0]  
bus with the contents of the addressed register while RDB and  
CSB are low.  
RDB shares the same pin as the LEN5[1] input. RDB is selected  
when HW_ONLY is tied low.  
Active Low Chip Select (CSB). CSB must be low to enable  
OCTLIU register accesses. CSB must go high at least once after  
power up to clear internal test modes. If CSB is not used, it  
should be tied to an inverted version of RSTB, in which case,  
RDB and WRB determine register accesses.  
CSB shares the same pin as the LEN5[2] input. CSB is selected  
when HW_ONLY is tied low.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
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