PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Pin Name
Type
Pin
No.
Function
RCLK[1]/EDATA[1]
RCLK[2]/EDATA[2]
RCLK[3]/EDATA[3]
RCLK[4]/EDATA[4]
RCLK[5]/EDATA[5]
RCLK[6]/EDATA[6]
RCLK[7]/EDATA[7]
RCLK[8]/EDATA[8]
Output
AA19 Recovered Clock Output (RCLK[8:1]). RCLK[8:1] is the clock
AA18 recovered from the RXTIP[8:1] and RXRING[8:1] input signals.
Y16
RCLK[8:1] share the same pins as the EDATA[8:1] outputs.
RCLK[8:1] are selected when SBI2CLK is tied low.
AA15
AB6
W7
W6
AB2
RDP[1]/DDATA[0]
RDP[2]/DDATA[1]
RDP[3]/DDATA[2]
RDP[4]/DDATA[3]
RDP[5]/DDATA[4]
RDP[6]/DDATA[5]
RDP[7]/DDATA[6]
RDP[8]/DDATA[7]
Output
AB19 Receive Digital Positive Data (RDP[8:1]). When in single rail
Y17
mode, RDP[8:1] output NRZ sampled DS-1 or E1 data which has
AB16 been decoded by AMI, B8ZS, or HDB3 line code rules. When in
AB15 dual rail mode, RDP[8:1] output NRZ sampled bipolar positive
W8
AA5
Y5
pulses.
RDP[8:1] can be updated on either the falling or rising RCLK[8:1]
edge.
W5
RDP[8:1] share the same pins as the DDATA[7:0] outputs.
RDP[8:1] are selected when SBI_EN and SBI2CLK are both tied
low.
Output
AB18 Receive Digital Negative Data/Line Code Violation Indication
AB17 (RDN/RLCV[8:1]). When in dual rail mode, RDN/RLCV[8:1]
RDN/RLCV[1]/IFP_OUT
RDN/RLCV[2]/EFP
RDN/RLCV[3]/C1FPOUT
RDN/RLCV[4]/DDP
RDN/RLCV[5]/DPL
RDN/RLCV[6]/DV5
W15
Y14
Y8
output NRZ sampled bipolar negative pulses. When in single rail
mode, RDN/RLCV[8:1] output a NRZ pulse whenever a line code
violation or excess zeros condition is detected.
AB5
AA4
Y4
RDN/RLCV[8:1] can be updated on either the falling or rising
RCLK[8:1] edge.
RDN/RLCV[7]/ECLK
RDN/RLCV[8]/DACTIVE
RDN/RLCV[8:1] share the same pins as the IFP_OUT, EFP,
C1FPOUT, DDP, DPL, DV5, ECLK and DACTIVE outputs.
RDN/RLCV[8:1] are selected when SBI_EN and SBI2CLK are
both tied low.
SBI System Side Interface
REFCLK/TDN[1] Input
W21
The SBI reference clock signal (REFCLK) provides reference
timing for the SBI ADD and DROP busses.
REFCLK is nominally a 50% duty cycle clock of frequency 19.44
MHz ±50ppm.
REFCLK shares the same pin as the TDN[1] input. REFCLK is
selected when SBI_EN or SBI2CLK is tied high.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
14
PMC [ PMC-SIERRA, INC ]
