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PM4318 参数 Datasheet PDF下载

PM4318图片预览
型号: PM4318
PDF下载: 下载PDF文件 查看货源
内容描述: 八进制E1 / T1 / J1线路接口设备 [OCTAL E1/T1/J1 LINE INTERFACE DEVICE]
分类和应用:
文件页数/大小: 244 页 / 2135 K
品牌: PMC [ PMC-SIERRA, INC ]
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PRELIMINARY  
PM4318 OCTLIU  
DATASHEET  
PMC- 2001578  
ISSUE 3  
OCTAL E1/T1/J1 LINE INTERFACE DEVICE  
Register 054H, 0D4H, 154H, 1D4H, 254H, 2D4H, 354H, 3D4H: CDRC Configuration  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
AMI  
0
0
0
0
0
0
0
0
LOS[1]  
LOS[0]  
Reserved  
Reserved  
ALGSEL  
O162  
Reserved  
Reserved:  
These bits must be a logic 0 for correct operation.  
O162:  
If the AMI bit is logic 0 in E1 mode, the Recommendation O.162 compatibility select bit  
(O162) allows selection between two line code violation definitions:  
If O162 is a logic 0, a line code violation is indicated if the serial stream does not match the  
verbatim HDB3 definition given in Recommendation G.703. A bipolar violation that is not part  
of an HDB3 signature or a bipolar violation in an HDB3 signature that is the same polarity as  
the last bipolar violation results in a line code violation indication.  
If O162 is a logic 1, a line code violation is indicated if a bipolar violation is of the same  
polarity as the last bipolar violation, as per Recommendation O.162.  
The O162 bit has no effect in T1 mode.  
ALGSEL:  
The Algorithm Select (ALGSEL) bit specifies the algorithm used by the DPLL for clock and  
data recovery. The choice of algorithm determines the high frequency input jitter tolerance of  
the CDRC. When ALGSEL is set to logic 1, the CDRC jitter tolerance is increased to  
approach 0.5 Uipp for jitter frequencies above 20 kHz. When ALGSEL is set to logic 0, the  
jitter tolerance is increased for frequencies below 20 kHz (i.e. the tolerance is improved by  
20% over that of ALGSEL=1 at these frequencies), but the tolerance approaches 0.4 Uipp at  
the higher frequencies.  
AMI:  
The alternate mark inversion (AMI) bit specifies the line coding of the incoming signal. A  
logic 1 selects AMI line coding by disabling HDB3 decoding in E1 mode and B8ZS in T1  
mode. In E1 mode, a logic 0 selects HDB3 line decoding which entails substituting an HDB3  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
130  
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