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PM4318 参数 Datasheet PDF下载

PM4318图片预览
型号: PM4318
PDF下载: 下载PDF文件 查看货源
内容描述: 八进制E1 / T1 / J1线路接口设备 [OCTAL E1/T1/J1 LINE INTERFACE DEVICE]
分类和应用:
文件页数/大小: 244 页 / 2135 K
品牌: PMC [ PMC-SIERRA, INC ]
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PRELIMINARY  
PM4318 OCTLIU  
DATASHEET  
PMC- 2001578  
ISSUE 3  
OCTAL E1/T1/J1 LINE INTERFACE DEVICE  
Register 045H, 0C5H, 145H, 1C5H, 245H, 2C5H, 345H, 3C5H:  
T1 XPDE Interrupt Enable/Status  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
R/W  
R/W  
R
STUFE  
STUFF  
STUFI  
PDV  
0
0
X
X
X
X
0
R
R
Z16DI  
PDVI  
R
R/W  
R/W  
Z16DE  
PDVE  
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.  
STUFE:  
The STUFE bit enables the occurrence of pulse stuffing to generate an interrupt on INTB.  
When STUFE is set to logic 1, an interrupt is generated on the occurrence of a bit stuff.  
When STUFE is a logic 0, bit stuffing occurrences do not generate an interrupt on INTB.  
STUFF:  
The STUFF bit enables pulse stuffing to occur upon detection of a violation of the pulse  
density rule. Bit stuffing is performed in such a way that the resulting data stream no longer  
violates the pulse density rule. When STUFF is set to logic 1, bit stuffing is enabled and the  
STUFI bit indicates the occurrence of bit stuffs. When STUFF is a logic 0, bit stuffing is  
disabled and the PDVI bit indicates occurrences of pulse density violation. Also, when STUFF  
is a logic 0, PCM data passes through XPDE unaltered.  
STUFI:  
The STUFI bit is valid when pulse stuffing is active. This bit indicates when a bit stuff  
occurred to eliminate a pulse density violation and that an interrupt was generated due to the  
bit stuff (if STUFE is logic 1). When pulse stuffing is active, PDVI remains logic 0, indicating  
that the stuffing has removed the density violation. The STUFI bit is reset to logic 0 once this  
register is read. If the STUFE bit is also logic 1, the interrupt is also cleared once this register  
is read.  
PDV:  
The PDV bit indicates the current state of the pulse density violation indication. When PDV is  
a logic 1, a violation of the pulse density rule exists. When PDV is a logic 0, no violation of  
the pulse density rule exists. Note: the PDV indication persists for the duration of the pulse  
density violation. At its minimum, PDV may be asserted for only 1 bit time, therefore, reading  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
112  
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