欢迎访问ic37.com |
会员登录 免费注册
发布采购

PM4318 参数 Datasheet PDF下载

PM4318图片预览
型号: PM4318
PDF下载: 下载PDF文件 查看货源
内容描述: 八进制E1 / T1 / J1线路接口设备 [OCTAL E1/T1/J1 LINE INTERFACE DEVICE]
分类和应用:
文件页数/大小: 244 页 / 2135 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM4318的Datasheet PDF文件第116页浏览型号PM4318的Datasheet PDF文件第117页浏览型号PM4318的Datasheet PDF文件第118页浏览型号PM4318的Datasheet PDF文件第119页浏览型号PM4318的Datasheet PDF文件第121页浏览型号PM4318的Datasheet PDF文件第122页浏览型号PM4318的Datasheet PDF文件第123页浏览型号PM4318的Datasheet PDF文件第124页  
PRELIMINARY  
PM4318 OCTLIU  
DATASHEET  
PMC- 2001578  
ISSUE 3  
OCTAL E1/T1/J1 LINE INTERFACE DEVICE  
Register 043H, 0C3H, 143H, 1C3H, 243H, 2C3H, 343H, 3C3H:  
T1 PDVD Interrupt Enable/Status  
Bit  
Type  
Function  
Default  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Unused  
Unused  
Unused  
PDV  
X
X
X
X
X
X
0
R
R
Z16DI  
PDVI  
R
R/W  
R/W  
Z16DE  
PDVE  
0
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.  
PDV:  
The PDV bit indicates the current state of the pulse density violation indication. When PDV is  
a logic 1, a violation of the pulse density rule exists. When PDV is a logic 0, no violation of  
the pulse density rule exists. Note: the PDV indication persists for the duration of the pulse  
density violation. At its minimum, PDV may be asserted for only 1 bit time, therefore, reading  
this bit may not return a logic 1 even though a pulse density violation has occurred.  
PDVI, Z16DI:  
The PDVI and Z16DI bits identify the source of a generated interrupt. PDVI is a logic 1  
whenever a change in the pulse density violation indication generated an interrupt. PDVI is  
cleared to 0 when this register is read. Z16DI is a logic 1 whenever 16 consecutive zeros are  
detected. Z16DI is cleared to 0 when this register is read. Note that the PDVI and Z16DI  
interrupt indications operate regardless of whether interrupts are enabled or disabled.  
Z16DE:  
The Z16DE bit enables an interrupt to be generated on the microprocessor INTB pin when 16  
consecutive zeros are detected. When Z16DE is set to logic 1, interrupt generation is  
enabled. When Z16DE is set to logic 0, interrupt generation is disabled.  
PDVE:  
The PDVE bit enables an interrupt to be generated on the microprocessor INTB pin when a  
change in the pulse density is detected. When PDVE is set to logic 1, an interrupt is  
generated whenever a pulse density violation occurs or when the pulse density ceases to  
exist. When PDVE is set to logic 0, interrupt generation by pulse density violations is  
disabled.  
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE  
111  
 复制成功!