PRELIMINARY
PM4318 OCTLIU
DATASHEET
PMC- 2001578
ISSUE 3
OCTAL E1/T1/J1 LINE INTERFACE DEVICE
Register 047H, 0C7H, 147H, 1C7H, 247H, 2C7H, 347H, 3C7H: T1 XIBC Loopback Code
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IBC7
IBC6
IBC5
IBC4
IBC3
IBC2
IBC1
IBC0
X
X
X
X
X
X
X
X
When the E1/T1B bit of the Global Configuration register is a logic 1, this register is held reset.
This register contains the inband loopback code pattern to be transmitted. The code is transmitted
most significant bit (IBC7) first, followed by IBC6 and so on. The code, regardless of the length,
must be aligned with the MSB always in the IBC7 position (e.g., a 5-bit code would occupy the
IBC7 through IBC2 bit positions). To transmit a 3-bit or a 4-bit code pattern, the pattern must be
paired to form a double-sized code (i.e., the 3-bit code ‘011’ would be written as the 6-bit code
‘011011’).
When the OCTLIU is reset, the contents of this register are not affected.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
115
PMC [ PMC-SIERRA, INC ]
