PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Registers 01BH, 05BH, 09BH and 0DBH: LCV_PMON Line Code Violation
Count MSB
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
Unused
LCV[12]
LCV[11]
LCV[10]
LCV[9]
X
X
X
X
X
X
X
X
R
R
R
R
R
LCV[8]
These registers indicate the number of LCV error events that occurred during the
previous accumulation interval. An LCV event is defined as the occurrence of a
Bipolar Violation or Excessive Zeros. The counting of Excessive Zeros (a string
of greater than: 3 consecutive zeros for E1 data, 7 consecutive zeros for B8ZS,
or 15 consecutive zeros for T1 AMI) can be disabled by the BPVCNT bit of the
Receive Configuration register (000H, 040H, 080H, and 0C0H).
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
81
PMC [ PMC-SIERRA, INC ]
