PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Registers 01EH, 05EH, 09EH and 0DEH: DJAT Output Clock Divisor (N2)
Control
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
N2[7]
N2[6]
N2[5]
N2[4]
N2[3]
N2[2]
N2[1]
N2[0]
0
0
1
0
1
1
1
1
These registers define an 8-bit binary number, N2, which is one less than the
magnitude of the divisor used to scale down the DJAT smooth output clock
signal. The output clock divisor magnitude, (N2+1), is the ratio between the
frequency of the smooth output clock and the frequency applied to the phase
discriminator input.
Writing to this register will reset the PLL and, if the SYNC bit is high, will also
reset the FIFO.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
84
PMC [ PMC-SIERRA, INC ]
