PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Registers 01FH, 05FH, 09FH and 0DFH: DJAT Configuration
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Unused
Unused
WIDEN
CENT
UNDE
OVRE
SYNC
LIMIT
X
X
1
0
0
0
1
1
R/W
R/W
R/W
R/W
R/W
R/W
These registers control the operation of the DJAT FIFO read and write pointers
and controls the generation of interrupt by the FIFO status.
WIDEN:
The WIDEN bit controls the width of the generated pulse from the XPLS
block. When WIDEN is set to logic 1, the high phase of one cycle of the 8X
clock generated by the DJAT PLL is modified to be nominally one 24X clock
period wider. This results in the XPLS producing a greater pulse width. When
WIDEN is set to logic 0, the smooth 8X clock from DJAT is not modified,
resulting in pulses of minimum allowable width (approx. 50% duty cycle).
These narrow pulses reduce the amount of energy sourced by the QDSX into
the line. The WIDEN bit has no effect when the DJAT PLL is not used.
CENT:
The CENT bit allows the FIFO to self-center its read pointer, maintaining the
pointer at least 4 UI away from the FIFO being empty or full. When CENT is
set to logic 1, the FIFO is enabled to self-center for the next 384 transmit data
bit period, and for the first 384 bit periods following an overrun or underrun
event. If an EMPTY or FULL alarm occurs during this 384 UI period, then the
period will be extended by the number of UI that the EMPTY or FULL alarm
persists. During the EMPTY or FULL alarm conditions, data is lost. When
CENT is set to logic 0, the self-centering function is disabled, allowing the
data to pass through uncorrupted during EMPTY or FULL alarm conditions.
CENT can only be set to logic 1 if SYNC is set to logic 0.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
85
PMC [ PMC-SIERRA, INC ]
