PM4314 QDSX
DATA SHEET
PMC-950857
ISSUE 5
QUAD T1/E1 LINE INTERFACE DEVICE
Register 009H:TOPS Master Clock Configuration/Clock Activity Monitor
Bit
Type
Function
Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R
R
TCLKIA[4]
TCLKIA[3]
TCLKIA[2]
TCLKIA[1]
XCLKA
X
X
X
X
X
X
0
R
R
R
R
CLKO8XA
XSEL[1]
R/W
R/W
XSEL[0]
0
This register provides activity monitoring on QDSX clock inputs and configures
the QDSX for the appropriate XCLK input. Figure 12 illustrates the different
timing configurations.
TCLKIA[4],TCLKIA[3],TCLKIA[2],TCLKIA[1]:
The TCLKIA[4:1] bits monitors for low to high transitions on the TCLKI[4:1]
inputs respectively. TCLKIA[X] is set high on a rising edge of TCLKI[X], and is
set low when this register is read.
XCLKA:
The XCLKA bit monitors for low to high transitions on the XCLK input.
XCLKA is set high on a rising edge of XCLK, and is set low when this register
is read.
CLKO8XA:
The CLKO8XA bit monitors for low to high transitions on the CLKO8X output.
CLKO8XA is set high on a rising edge of CLKO8X, and is set low when this
register is read.
XSEL[1:0]:
The XSEL[1:0] bits configures the QDSX for the desired XCLK input and for
the CLKO8X/CLK01X output according to the following table:
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
69
PMC [ PMC-SIERRA, INC ]
